| Publisher | Hitachi Data Systems | ||
|---|---|---|---|
| Format | 237.7KB PDF | Date added | 21 Feb 2009 |
| Topics | Microprocessors, Processors, Mainframes | ||
| Downloads | 3 | ||
The performance results presented just demonstrates how the fourth generation of Universal Star Network Crossbar switch architecture has been built to scale and perform in the most demanding situations. It says how without saturating the Microprocessors in the Host Channel PCB it have achieved read and write cache hit IO rates of 365K and 381K respectively, which shows the potential to achieve a half million IOPS.
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