| Publisher | Association for Computing Machinery | ||
|---|---|---|---|
| Format | 400.9KB PDF | Date added | 25 Oct 2006 |
| Topics | Microprocessors | ||
| Downloads | 6 | ||
The sustained push toward smaller and smaller technology sizes has reached a point where device reliability has moved to the forefront of concerns for next-generation designs. Silicon failure mechanisms, such as transistor wearout and manufacturing defects, are a growing challenge that threatens the yield and product lifetime of future systems. This paper introduces the BulletProof pipeline, the first ultra low-cost mechanism to protect a microprocessor pipeline and on-chip memory system from silicon defects. To achieve this goal they combine area-frugal on-line testing techniques and system-level checkpointing to provide the same guarantees of reliability found in traditional solutions, but at much lower cost.
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