| Publisher | Koninklijke Philips Electronics | ||
|---|---|---|---|
| Format | 123.0KB PDF | Date added | 06 Oct 2006 |
| Topics | Processors | ||
| Downloads | 1 | ||
Low power design of the digital SoC (System on a Chip) is a hot research area recently. The power estimation techniques can be implemented at all abstraction levels in the low power design flow, of which system level is on the top. The power estimation in this level can greatly save the designer's effort and time of going to the lower design levels. However, in system level, the detailed information about the circuit of the system cannot be extracted.
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