| Publisher | University of Arizona | ||
|---|---|---|---|
| Format | 200.4KB PDF | Date added | 01 Oct 2007 |
| Topics | Optical Networking, Processors | ||
| Downloads | 4 | ||
In a Symmetric MultiProcessor (SMP), every processor has its own cache, and all the processors and memory modules are connected to the central interconnect, which is usually a shared bus. As the processors become faster, the central interconnect architecture of traditional SMP's impedes performance because it cannot keep up with the processors capabilities. As SMP's have hardware-enforced cache coherence, the snoop bandwidth required for address translation becomes the bottleneck. The growing performance gap between the processor speed and the conventional metal interconnection technology provides the impetus to look at optical technology for solutions. The emerging feasibility of optical interconnects is very promising for signal transmission in digital systems with high data rates at the board level and backplane.
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