| Publisher | University of Bucharest | ||
|---|---|---|---|
| Format | 1.2MB PDF | Date added | 18 Dec 2002 |
| Topics | Ethernet, Switching, Fast Ethernet | ||
| Downloads | 0 | ||
This paper reports recent work on Ethernet traffic generation and analysis. The paper uses Gigabit Ethernet NICs running custom firmware and custom-built 32-port Fast Ethernet boards based on FPGAs to study the behavior of large Ethernet networks. The traffic generation software is able to accommodate many traffic distributions with the ultimate goal of generating traffic that resembles the data collection system of the ATLAS experiment at CERN. A fraction of the 1600 ATLAS detector readout buffers and 600 Level 2 trigger CPUs are emulated in this study with a combination of the Fast Ethernet boards and the Gigabit Ethernet NICs. Each packet is time stamped with a global clock value and therefore the paper is able to compute an accurate measure of the network latency.
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