| Publisher | University of Tehran | ||
|---|---|---|---|
| Format | 1.0MB PDF | Date added | 12 Sep 2005 |
| Topics | Switching, Bandwidth Issues | ||
| Downloads | 11 | ||
In high-speed network switches and routers, packet memories have to allow line-speed buffering of data packets. With today's growing network line-rates, memory bandwidth is an essential constraint to build high-speed network buffers. This paper proposes a methodology for designing high-performance network-specific memories using slower lower-cost building blocks. They use parallel memory devices to increase the bandwidth. One possible problem of such architecture is inefficient usage of memory capacities due to division of buffering space between two or more memory pieces. They have concluded that this problem arises from the fact that numbers of accesses to memory blocks are imbalanced due to random nature of packet arrivals and departures.
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