| Publisher | Georgia Institute of Technology | ||
|---|---|---|---|
| Format | 217.5KB PDF | Date added | 03 Apr 2007 |
| Topics | Scalability, Microprocessors | ||
| Downloads | 4 | ||
Three-Dimensional integration provides a simultaneous improvement in wire-related delay and power consumption of microprocessor circuits. Prior work has looked at the performance, power, and area benefits of the 3D integration technology. This paper investigates the scalability issues of 3D die-stacked arithmetic units. It explores the behavior of the 3D-integrated arithmetic circuits with increasing issue-width (parallel execution capability), transistor sizing, and temperature. The paper shows that the 3D-integrated units have a lower latency degradation and lower rate of increase in energy consumption than the planar circuits with increasing issue-widths and operating temperatures. It demonstrates that the 3D-integrated circuits have less sensitivity to transistor sizing than the planar circuits. The better scalability of 3D circuits may extend the silicon roadmap for a few more generations.
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