With CMOS technology scaling down to the nanometer realm, process variations have been increased. In particular, the increase of delay variations has seriously affected the design periods and timing yields. To estimate more accurately these delay variations, Statistical Static Timing Analysis (SSTA), which considers delay variations statistically, has been proposed. SSTA is expected to shorten the design Turnaround Time (TAT) and predict the timing yields. Research on practical applications of SSTA has already been conducted at Fujitsu Laboratories. The paper has developed SSTA tools for use in designs for processors and Application Specific Integrated Circuits (ASICs) in cooperation with Fujitsu and Fujitsu VLSI. This paper describes the delay variations and basic SSTA techniques and introduces SSTA applications to Fujitsu's processor and ASIC design flows.
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