| Publisher | Stanford University | ||
|---|---|---|---|
| Format | 366.4KB PDF | Date added | 15 May 2007 |
| Topics | Quality of Service, Network Design | ||
| Downloads | 7 | ||
As Systems-on-Chip (SoC) become more prevalent, and as computer architecture as a whole makes a shift to more modular and parallel designs, on-chip interconnection networks are seen more and more frequently,. As with all aspects of microprocessor design, as the problem size and design space grows, arriving at an efficient solution by hand quickly becomes intractable. It becomes necessary to automate the design process. This principle applies to interconnection networks as well. The interconnection network field is fairly developed; however, only in recent years has semiconductor technology provided enough transistors on a single chip to make on-chip networks a possibility.
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