| Publisher | Kyushu University | ||
|---|---|---|---|
| Format | 1009.6KB PDF | Date added | 15 Jun 2007 |
| Topics | Local Area Networks (LAN), Wireless LAN | ||
| Downloads | 7 | ||
In Direct Conversion Receiver (DCR) architecture, the design of mixer is one of the most important steps for a high-performance DCR because it involves the issues of flicker (1/f) noise and conversion gain simultaneously. So, minimizing 1/f noise while achieving high gain without sacrificing linearity for high performance DCR is one of the critical issues. A method to reduce noise factor of a down-conversion mixer by 5-6 dB and to increase conversion gain by 5-6 dB simultaneously has been proposed. In order to reduce the chip size, on-chip CPW lines has been employed to realize on-chip impedance matching circuits which saves 30-40% chip area than those using the spiral inductors.
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