| Publisher | Institute of Electrical and Electronics Engineers | ||
|---|---|---|---|
| Format | 582.5KB PDF | Date added | 23 Aug 2007 |
| Topics | ASICs - Chip Sets, Mobile - Wireless Communications | ||
| Downloads | 41 | ||
Architectures for wireless systems have traditionally been designed to meet real-time requirements, t on a limited die area, and operate within a low power budget. These conditions are usually met by implementing compute-intensive operations in an Application Specific Integrated Circuit (ASIC). ASIC design is both expensive and time consuming. ASICs also suffer in that even minor evolutionary changes in the application invoke another ASIC design cycle. In the rapidly evolving wireless communication space these defects are severe. Flexibility can be achieved by reconfigurable architectures, and the ability to use special purpose configurations enhances both performance and energy efficiency. Often reconfigurable systems are based on FPGA devices which compromise both logic speed and power in order to achieve reconfigurability.
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