In this white paper, IDC examines the current environment surrounding the development of the Intel Xeon-based Extended Memory 64 Technology (EM64T) chip, code named "Nocona," for the x86 server market. In addition, this paper also reviews the adoption of 64-bit computing in the x86 market, how this technology further enables the move toward industry standards, as well as the design point differentiation IBM is targeting.
Related white papers
Understanding USB Flash Drives as Portable Infrastructure
The purpose of this white paper is to briefly discuss seven important topics everyone in business needs to know about USB flash drives. More importantly, this white paper is meant...
TMS320C6000 EMIF: Overview of Support of High Performance Memory Technology
This document gives an overview of the memory technologies currently available in the semiconductor industry. It highlights the tradeoffs in memory selection in a TMS320C6000™ External Memory Interface (EMIF) based...
DDR Memory Technology
In the last few years, a tremendous upsurge has occurred in the evolution of DRAM technology. Where originally, nearly all PC system memory was confined to FPM (Fast Page Mode)...
Intel 915G Express Chipset
Learn how the Intel Express Chipset can integrate several advancements to address the demands of evolving software, including next-generation memory capabilities.
Performance Comparison: Intel® Itanium® 2-Based Servers Running SAS 9
The Cornell Institute for Social and Economic Research (CISER) set out to increase the performance of some of its processing- and memory-intensive SAS applications. CISER had to acquire the...
Memory Technology Evolution
The purpose of this paper is to discuss the evolution of main and graphics memory technologies in relation to Compaq products. This paper should help alleviate some of the confusion surrounding the...
The Price of Safety: Evaluating IOMMU Performance
IOMMUs, IO Memory Management Units, are hardware devices that translate device DMA addresses to machine addresses. An isolation capable IOMMU restricts a device so that it can only access parts...


