With maturing compiler technologies, compile-time analysis can be a very powerful tool for optimizing code on any architecture. In combination with runtime performance analysis, the compiler becomes the most effective tuning tool. The methods described in this paper can be applied to any parallel architecture with multiple microprocessor execution units. This paper discusses the philosophy behind key performance parameters of the Intel Itanium architecture and their functions that factor in the performance modeling formulas. The paper provides a slightly different angle on performance modeling and analysis of parallel architectures. It explores a compile-time based approach for predicting performance of compute intensive code blocks on Intel Itanium architecture.
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