Chip multi-threading processor technology is key to the approach of maximizing overall workload throughput rather than the speed of a single thread of execution. CMT technology, like that available in the UltraSPARC T1 processor, provides a new thread-rich environment that drives application throughput and processor resource utilization while effectively masking memory access latencies. This new processor design provides multiple physical-instruction execution pipelines and several active thread contexts per pipeline. Akin to symmetric multiprocessing on a chip, UltraSPARC T1 processors are designed so that applications that currently scale well on SMP machines are likely to scale well in UltraSPARC T1 processor-based environments. Simple modifications, including those discussed in this paper, often result in even greater scalability.
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