High-performance computing engines often provide product-defining functionality within consumer devices. These devices are traditionally implemented using either ASICs or embedded processors. ASICS are inflexible and require high design cost while embedded processors provide inadequate compute power and efficiency for specialized applications. This paper describes the ACRES (Architecture and Compiler for REconfigurable Systems) platform that combines the flexibility of a programmable technology and the efficiency of custom hardware without incurring high-cost, high-risk chip development. The ACRES platform consists of a programmable computing fabric architecture and an associated spatial compiler. This paper describes the motivating assumptions, key ideas and technologies advocated in the ACRES platform.
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