| Publisher | Rice University | ||
|---|---|---|---|
| Format | 165.4KB PDF | Date added | 06 Jun 2005 |
| Topics | Mobile - Wireless Communications, TDMA - CDMA | ||
| Downloads | 96 | ||
This paper proposes a novel low power and low complexity multi-stage Parallel-Residue-Compensation (PRC) architecture for enhanced MAI suppression in the CDMA systems. The accuracy of the interference cancellation is improved with a set of weights computed from an adaptive Normalized Least-Mean-Square (NLMS) algorithm. The physical meaning of the complete versus weighted interference cancellation is applied to clip the weights above a certain threshold. Multistage Convergence-Masking-Vector (CMV) is then proposed to combine with the clock gating as a dynamic power management scheme in the VLSI receiver architecture.
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