Decoding of forward error correcting (FEC) codes is the most computationally intensive part of symbol-rate processing in a basestation receiver and could consume up to 90% of computing resources. This is true for both second generation (2G) and third generation (3G) systems. This paper compares three different implementation options for decoding in 3G wireless - software approach using DSPs, hardware approach using ASICs, and a combined software-hardware approach using on-chip accelerators.
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