| Publisher | IBM | ||
|---|---|---|---|
| Format | 990.0KB PDF, requires Acrobat Rdr 5 | Date added | 21 Jan 2005 |
| Topics | ASICs - Chip Sets, Microprocessors | ||
| Downloads | 7 | ||
This paper compares interconnect measurements with estimates for control logic in individual designs, in functional units, and in the entire POWER4 core. The results presented in this paper show that the estimates are typically lower than the actual wire-length measurements. The results also show that the estimates of the total wire-length for all of the control logic in the POWER4 agree to within 31% of the total measured wire-length.
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