Impediments to main memory performance have traditionally been due to the divergence in processor versus memory speed and the pin bandwidth limitations of modern packaging technologies. This paper evaluates a magneto-resistive memory (MRAM)-based hierarchy to address these future constraints. MRAM devices are nonvolatile, and have the potential to be faster than DRAM, denser than embedded DRAM, and can be integrated into the processor die in layers above those of conventional wiring.
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