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Validating Timed UML Models by Simulation and Verification

PublisherIMAG
Format269.6KB PDF, requires Acrobat Rdr 5Date added09 Jul 2004
Topics UML, Software Engineering, Object-Oriented
Downloads42

This paper presents a technique and a tool for model-checking operational (design level) UML models based on a mapping to a model of communicating extended timed automata. The target language of the mapping is the IF format, for which existing model-checking and simulation tools can be used. The approach presented in this paper takes into consideration most of the structural and behavioral features of UML, including object oriented aspects.

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