DDR SDRAMs break with the traditional system synchronous clocking approach, that uses only one global and skewless clock distribution network. The application of DDR SDRAMs requires a source synchronous clocking concept that simultaneously transmits clock and data signals from the memory controller to the DDR SDRAM devices. From the perspective of this source synchronous clocking concept, many timing problems disappear and using DDR SDRAMs is quite straightforward. This paper discusses a clocking strategy for a DDR SDRAM Controller IP implemented in a Xilinx Virtex-II-Pro FPGA.
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