| Publisher | University of Maryland | ||
|---|---|---|---|
| Format | 783.0KB PDF, requires Acrobat Rdr 5 | Date added | 01 Nov 2001 |
| Topics | Memory Components, Workstations | ||
| Downloads | 2 | ||
This paper presents a simulation-based performance study of several of the new high-performance DRAM architectures, each evaluated in a small system organization. These small-system organizations correspond to workstation-class computers and use only a handful of DRAM chips (~10, as opposed to ~1 or ~100). The study covers Fast Page Mode, Extended Data Out, Synchronous, Enhanced Synchronous, Double Data Rate, Synchronous Link, Rambus, and Direct Rambus designs.
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