The amount of data traffic through the IP backbone is doubling every year. This means that it is no longer reasonable to expect network data processing systems to keep pace with performance requirements through improvements to large-scale integration processes only. To meet these application requirements, NEC Electronics provides complete solutions for 10 Gbps line cards in OC-192c/STM-64c systems and 10 Gbps Ethernet systems. Together, the 200-MHz random access embedded DRAM and newly developed Optical Internetworking Forum (OIF)-compliant System Packet Interface Level-4 Phase 2 (SPI4.2) interface core promise lower power consumption, higher memory integration, higher speed, and lower soft error rates. The efficiency of these solutions has been proven in the evaluation chip described in this paper.
Did you find this white paper useful?
27 out of 50 users found this white paper useful
Related white papers
TMS320C6000 EMIF: Overview of Support of High Performance Memory Technology
This document gives an overview of the memory technologies currently available in the semiconductor industry. It highlights the tradeoffs in memory selection in a TMS320C6000™ External Memory Interface (EMIF) based...
DDR Memory Technology
In the last few years, a tremendous upsurge has occurred in the evolution of DRAM technology. Where originally, nearly all PC system memory was confined to FPM (Fast Page Mode)...
Intel 915G Express Chipset
Learn how the Intel Express Chipset can integrate several advancements to address the demands of evolving software, including next-generation memory capabilities.
Performance Comparison: Intel® Itanium® 2-Based Servers Running SAS 9
The Cornell Institute for Social and Economic Research (CISER) set out to increase the performance of some of its processing- and memory-intensive SAS applications. CISER had to acquire the...
Memory Technology Evolution
The purpose of this paper is to discuss the evolution of main and graphics memory technologies in relation to Compaq products. This paper should help alleviate some of the confusion surrounding the...
The Price of Safety: Evaluating IOMMU Performance
IOMMUs, IO Memory Management Units, are hardware devices that translate device DMA addresses to machine addresses. An isolation capable IOMMU restricts a device so that it can only access parts...
New DDR2 Memory Offers Advantages for Dual-Processor Servers
Technology innovation across platform subsystems is necessary to keep computing platforms in balance. DDR2 is the next logical progression for memory standards and speeds, and is considered one of most...
