This paper describes some of the important characteristics of the POWER2 architecture implementations. All POWER2 architecture implementations are completely binary compatible. The POWER2 architecture is also upward binary compatible with the IBM POWER architecture. The major differences discussed in this paper are data cache size, second level cache (L2 cache) and memory interface and processor interface (processor to data cache interface) widths. These characteristics result in different levels of performance impact for three classes of codes: Integer, Floating Point and Commercial Transaction Processing.
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