The POWER version of the RS/6000 Floating-Point Unit (FPU) set a new standard for floating-point performance. Its innovative multiply- add fused (MAF) dataflow minimizes latency, rounding error, and chip busing. The MAF unit performs a double-precision multiply in a single cycle and a double-precision add in the following cycle. A single round occurs in the final and bypassable stage of the pipeline. The FPU combines, in a single two-stage pipeline, capabilities which many other processors, such as the SuperSPARC Microprocessor, provide with two units, usually a separate multiplier and adder.
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