| Publisher | IBM | ||
|---|---|---|---|
| Format | HTML | Date added | 08 Jul 2004 |
| Topics | ASICs - Chip Sets, Processors | ||
| Downloads | 15 | ||
The multichip POWER2 processor implementation provides industry leading performance in both floating-point and fixed-point applications. Three of the chips on the multichip module, the Fixed-Point Unit (FXU), Data Cache Unit (DCU), and Storage Control Unit (SCU), provide a tightly integrated subsystem that avoids bottlenecks in the cache, memory, and I/O interfaces. The balanced system design allows POWER2 systems to excel on both technical and commercial applications. The FXU, DCU, and SCU functionality and system structure are similar to those in a POWER implementation. This paper presents the FXU, DCU, and SCU designs, as well as the memory and I/O interfaces, found in the POWER2 system.
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