| Publisher | University of Patras | ||
|---|---|---|---|
| Format | 51.2KB PDF | Date added | 26 May 2002 |
| Topics | Mobile - Wireless Communications, Wireless LAN | ||
| Downloads | 195 | ||
In this paper, a VLSI implementation for the SAFER+ encryption algorithm is presented. The combination of security, and high speed implementation, makes SAFER+ a very good choice for wireless systems. The SAFER+ algorithm is a basic component in the authentication Bluetooth mechanism. The relation between the algorithm properties and the VLSI architecture are described. The whole design was captured entirely in VHDL language using a bottom-up design and verification methodology. FPGA device was used for the hardware implementation of the algorithm.
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