The turbo encoder/decoder (codec) forward error correction (FEC) demonstration is designed to show the capabilities of the Altera® turbo encoder/decoder MegaCore® function in correcting errors. The demonstration is for use with the system-on-a-programmable-chip (SOPC) board and uses the 32-bit Nios family of soft-core embedded processors.
The SOPC board includes an APEX™ 20K400E device and an LCD, which allows you to monitor the demonstration. The Nios embedded processor sets up the codec, controls the channel error rate, and collates and displays the error information on the LCD.
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