For large or complex System-on-a-Chip designs, which often consist of over one million gates, full chip gate-level dynamic simulation is becoming increasingly time consuming and verification coverage is steadily diminishing. LSI uses static timing analysis to ensure that a design will meet timing. Synopsys PrimeTime has been qualified for static timing analysis signoff within the LSI Logic Flexstream flow. Designers in the past have spent a huge portion of their overall design time performing functional and timing verification of the design. Using dynamic verification method, a designer would have to create an extremely large number of timing vectors to verify the timing paths in the design. As the size and complexity of designs increase however it’s becoming almost impossible for a designer to create such a vector set to achieve complete coverage.
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