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Analysis of a Memory Architecture for Fast Packet Buffers

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12 out of 26 users found this white paper useful


Publisher Stanford Knowledgebase
Publisher Registration Direct Access
Topics ATM, Memory Components Date added 02 Apr 2001
Downloads 3 Format 37.0KB PDF, requires Acrobat Rdr 5

A fundamental requirement of a packet switch (e.g. an Internet router or ATM switch) is its need to buffer packets. Often, the performance of a packet switch is limited by the speed at which it can buffer packets. This paper is about one practical method to overcome this limitation. There are, in fact, several approaches to this problem but due to the proprietary nature of different commercial solutions, people are not aware of any quantitative analysis or comparison of different techniques. While this paper describes and analyzes one packet buffer architecture, it is the longer term goal of the work to quantitatively compare a variety of techniques.

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12 out of 26 users found this white paper useful


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