| Publisher | Switchcore Technology | ||
|---|---|---|---|
| Format | 177.0KB PDF, requires Acrobat Rdr 5 | Date added | 01 Feb 2001 |
| Topics | ASICs - Chip Sets | ||
| Downloads | 1168  popular | ||
The performance of a switch is measured on how well it can move packets from input to output ports. Due to the inherent burstiness of "real" traffic, a switch's performance is also measured on its ability to store packets when the switch fabric and/or an output port is temporarily overloaded. These packets are stored in packet buffer memory. It is necessary for every system designer to offset the cost of buffer memory against the switch performance. To this end, it is necessary to consider all the different factors affecting the amount of packet buffer needed per port in a switching solution. This paper seeks to cover these factors by discussing such topics as memory architectures, switch fabric throughput, memory utilization and switch chip latency and the effect that these factors have on the traffic handling capabilities, and hence the performance, of a switch.
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