| Publisher | Magma Design Automation | ||
|---|---|---|---|
| Format | 902.2KB HTML & PDF | Date added | 18 Mar 2004 |
| Topics | Semiconductor Tech. - Manufacturing, ASICs - Chip Sets | ||
| Downloads | 186 | ||
The unsatiated consumer demand for products that are smaller, faster, cheaper, and have increased functionality is driving the Digital Design Age of the 21st century. However, companies designing the chips that go into these new products are facing huge problems taking designs from RTL to silicon in the narrow, two-to-three month market windows required to stay competitive. Simply stated, there is a crisis when it comes to taking the functional description of a device and physically laying out, routing, and implementing the device. This crisis has a number of related sources, all of which have been discussed ad nauseaum the EDA industry. It’s always the same story: deep sub-micron (DSM) forces physical design to move into the logical design space. Fix that and you fix the problem. Unfortunately, the industry is discovering that this problem is not so easily fixed. Simply promoting physical knowledge to the front-end of the design process may reduce layout-to-synthesis iterations, but it doesn’t eliminate them. And when market windows shrink to a few weeks from product conception to introduction, iterations, no matter how few, will mark the failure of many companies. In fact, the industry knows that the only way to solve the crisis is to create new digital IC design technologies that specifically address DSM from the ground up. But this is too expensive for EDA companies that have been in the digital IC design business for many years, because their existing technologies have too many legacy issues. One of the key problems is that their underlying tool architectures are ten to fifteen years old and can only be enhanced to a certain degree. The core limitations in these architectures have rendered these tools non-scaleable for processes of 0.18-microns and below.
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