In the next couple of years programmable logic will be taken into a new era with the introduction of 0.25micron and 0.18micron geometries. Changes in the design flow are necessary due to many of the issues that surfaced in the design of deep submicron Integrated Circuits a few years ago. Even though many of these issues are related, the design tools that address the issues of designing high complex programmable devices will have to be different from the ones that solved the problems within the ASIC community. The paper will review the techniques necessary to achieve good quality of results with today's technologies, such as understanding the target architectures, synthesis and timing budget management. It will also open up discussions on what is needed to solve the problems presented by Complex programmable logic devices as they surpass 100K usable gates. This will include tighter integration between the synthesis technology and the place & route tools so that there is a stronger link between logical and physical design. Hardware Description Languages (HDLs) and synthesis have become the preferred way of describing high complex programmable devices. Therefore to achieve the performance from these devices, new tools are needed to allow the partitioning and floorplanning of these devices at the Register Transfer Level (RTL). This paper will discuss the impact of failing to consider floorplanning and hierarchy when using an HDL.
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