| Publisher | Synplicity | ||
|---|---|---|---|
| Format | PDF, requires Acrobat Rdr 5 | Date added | 14 Aug 2003 |
| Topics | Bandwidth Issues | ||
| Downloads | 10 | ||
Verification is the biggest bottleneck for today™s complex ASIC designs. Continually advancing process technology, and the corresponding explosion in design size and complexity, have lead to verification problems that are impossible to solve using traditional software simulation tools. In addition, an increasing number of applications that process large quantities of data in real time (such as video) require verification techniques that run at near real-time speeds. As a result, a growing number of ASIC designers are building prototype boards using FPGAs to verify their ASIC designs. Another advantage of building prototype boards using FPGAs is that it allows software development and debugging to happen in parallel with the design and debug of the final ASIC, reducing time to market. ASIC designers face several challenges in prototyping and debugging the design using FPGAs. One of the biggest challenges is that the capacity of even the largest FPGAs is much smaller than the size of a complex ASIC. This means that designers must struggle to partition their design into multiple FPGAs, with no tools to help them make good partitioning decisions, and no way to model the characteristics of the prototype board during synthesis and partitioning. Iterations between synthesis, partitioning, and board implementation are time-consuming and tedious. Because of the enormous time to market pressures System-on-Chip and other devices with software content face, it is no longer possible to delay software development until working devices are available. Hardware-software co-design is imperative. The EDA industry is responding by producing new tools and approaches. High level description languages and improved libraries have dramatically improved designer productivity. The rise of IP cores have allowed the designer to use proven elements to build large sections of the design quickly and confidently. The bottleneck comes from verifying that the ASIC design is correct before moving to p
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