| Publisher | Philips | ||
|---|---|---|---|
| Format | 120.8KB PDF, requires Acrobat Rdr 5 | Date added | 30 Dec 2003 |
| Topics | Memory Components, Interfaces / Buses / I/Os | ||
| Downloads | 2 | ||
A common pitfall in the design of high-performance imaging systems, particularly systems employing scalable multiprocessor architectures, is the failure to balance computational and memory bandwidth with I/O. The recent introduction of microprocessors with large internal caches and high-performance external memory interfaces make it practical to design high-performance imaging systems with balanced computational and memory bandwidth. In these systems, both the board level memory and I/O architecture as well as the microprocessor memory have significant performance impact. Systems that do not scale the memory bus bandwidth as processors are added do not typically improve in performance, or they reach a limiting value after some initial small gains in performance. In addition, the I/O bandwidth plays a significant role in overall performance.
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